RM0319 datasheet(33/368 Pages) STMICROELECTRONICS

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RM0319

Multilayer interconnect matrix (BUSMATRIX)

Doc ID 022640 Rev 3

33/368

Figure 4.

ICM block diagram

A layer is referred to as one or more masters that compete with one master to win ownership

of the slave.

When there is more that one layer looking for access to the slave at the same time, this is

referred to as a clash of requests. Whenever a clash is detected, only one layer can gain

access to the slave. The layer that does not gain access to the slave needs to have its

address and control signals stored into their input stage. When address and control signals

are stored into an input stage, then the stored transfer controls the request and lock

generation circuitry. When a lower priority layer is in the middle of a burst transfer and a

higher priority layer issues a transfer, the higher priority layer is stored and then held off until

the lower priority layer completes the transfer.

Table 5 shows the master layer on each ICM input stages while Table 6 lists the ICM slaves.

Table 5.

ICM master layers (Initiators)

ICM

Processor

RAS_H

DMAC Master 1

Processor

RAS_H

DMAC Master 2

Processor

RAS_H

Processor

RAS_H

5RAS_H

DMA Master 1

Ethernet MAC

USB (Hosts - Device)

Ras_E

DMAC Master 2

Ethernet MAC

USB (Hosts - Device)

Table 6.

ICM slaves (targets)

ICM

Sbs_LowSpeed

Sbs_Application

ICM

AHB

MASTER

Arbiter

priority

AHB

(Layer 0)

AHB MASTER

(Layer N)

SLAVE

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