RM0319 datasheet(98/368 Pages) STMICROELECTRONICS

98 / 368 page

Serial NOR Flash controller (SMI)

RM0319

98/368

Doc ID 022640 Rev 3

When the 2 conditions above are met, the following data sequence is sent to the bank

selected by AHB address bits [24-25]:

●

Page program instruction opcode (8’h02,Table 34),

●

3- or 2-byte address (depending on the ADD_LENGTH bit of SMI_CR1 register from

the MSB to the LSB,

●

All data bytes (from bit 7 to bit 0) are transferred, starting with the address given in the

previous step and incrementing it to the last depending on the size of the write request.

After a write request has been sent, the WM bit in SMI_SR register is cleared and the read

status register instruction (opcode 8’h05, Table 34) is automatically sent to this bank until no

write in progress (WIP =1‘b0).

Note:

The write capability must be used only if there is a write in progress, which means that a

busy bit of the external memory status register is located in bit 0. Otherwise, the system will

become locked.

When the memory programming is finished, the WCF bit in the SMI_SR register is set and

an interrupt is generated if the enabling WCIE bit in the SMI_CR1 register is set.

In order to send a write request to a bank other than the one under programming, the

software must wait for WIP = 1‘b1, otherwise the error ERF2 would be generated due to non

incrementing address. The bank under programming phase must not be disabled in order to

write to another one.

Write burst mode

Write burst mode (WBM bit set in SMI_CR1 register) enables to keep selected the external

SPI memory after an AHB write request (see above). In this case, the next AHB write

request should point to the next incremented address and should have the same size (byte,

half-word or word). Otherwise, an error flag is set (ERF2 flag in the SMI_SR register, and an

ERROR response is sent back to the AHB master.

Note:

A memory access error (ERF1 or ERF2) results in both release of chip select and start of

the external memory page program.

Disabling the write burst mode (that is, clearing the WBM bit in SMI_CR1 register), the next

incrementing AHB write request should be sent to external memory if it occurs before the

end of the previous serial transfer. Otherwise, an error flag is set (ERF2 flag in the SMI_SR

Consequently, it is mandatory to enable the write burst mode in order to perform several

write requests which are not sent in the same AHB incrementing burst. If WBM is cleared

and no other write request occurs, the external memory selection is released after sending

the data and the external memory page program cycle starts.

Note:

Read requests to external memory are not allowed in write burst mode, otherwise an error

flag is set (ERF1 flag in the SMI_SR register) and an ERROR response is sent back to the

AHB master.

The external SPI memory is released by either disabling write burst mode (clearing WBM

bit) or disabling the bank, and the external memory page program cycle starts. If bank is

enabled, read status register instruction is automatically sent to this bank until WIP = 1‘b0.

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