RM0319 datasheet(102/368 Pages) STMICROELECTRONICS

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Parallel NAND Flash controller (FSMC)

RM0319

102/368

Doc ID 022640 Rev 3

8.3

Functional description

Figure 23.

FSMC block diagram

8.3.1

AHB interface

The AHB interface block provides the FSMC interface to the AHB bus. It decomposes the

system bus transfers into external accesses supported by the selected external device.

The RW control register values are accessed through the AHB, and their values are passed

to the rest of the peripherals

The following conditions cause an ERROR response:

●

If a disabled external device is accessed.

●

If a Flash memory is accessed when its Reset Powerdown bit (GenMemCtrl_PC(i)

registers) has been set to 0.

●

If HSIZE is greater than 2, which means a transfer size larger than 32 bits. In other

cases, OKAY response is returned.

The AHB interface does not support the following AHB features:

●

It does not generate SPLIT or RETRY responses.

●

Protection control is not implemented, which means that HPROT is not connected.

8.3.2

NAND Flash controller

This block interfaces the AHB interface block to the external NAND Flash. For NAND Flash,

the following types of accesses are supported:

Common memory space access

It is the normal way of accessing the NAND Flash. The data size is specified in the

DevWidth field of configuration register (GenMemCtrl_PC register), and the corresponding

timings must be specified in the GenMemCtrl_Comm register. The data used while

accessing this region is passed to D(7:0) bits (or D(15:0) according to the Flash memory

bus width). The FSMC_ADDR_LE or FSMC_CMD_LE pins are used to drive directly ALE

and CLE, respectively. Therefore, by accessing particular regions of the common memory

space, we can send to the NAND Flash a command (CLE high) or an address (ALE high).

Configuration

Registers

AHB

Interface

NAND Flash

Driver

AHB

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