2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or

28-Port I/O Expander

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11

The MAX7300 maintains an internal 7-bit snapshot reg-

ister to hold the comparison copy of the logic states of

ports P24 to P30. The snapshot register is updated with

the condition of P24 to P31 whenever the configuration

register is written with the M bit set. The update action

occurs regardless of the previous state of the M bit so

that it is not necessary to clear the M bit and then reset

it in order to update the snapshot register.

When the data change detection bit is set, the MAX7300

continuously compares the snapshot register against

the changing states of P24 to P31. When a difference

occurs, the IRQ bit (mask register bit D7) is set and IRQ

port P31 goes high if it is configured as an output.

The IRQ bit and IRQ output remain set until the mask

register is next read or written, so if the IRQ is set, then

the mask register reads with bit D7 set. Writing the

mask register clears the IRQ bit and resets the IRQ out-

put, regardless of the value of bit D7 written.

internal biasing. Use a resistor value of 39k

Ω.

Applications Information

Low-Voltage Operation

The MAX7300 operates down to 2V supply voltage

(although the sourcing and sinking currents are not

guaranteed), providing that the MAX7300 is powered up

initially to at least 2.5V to trigger the device’s internal

reset.

Power-Supply Considerations

The MAX7300 operates with power-supply voltages of

2.5V to 5.5V. Bypass the power supply to GND with a

0.047µF capacitor as close to the device as possible.

Add a 1µF capacitor if the MAX7300 is far away from

the board’s input bulk decoupling capacitor.

Chip Information

TRANSISTOR COUNT: 33,559

PROCESS: CMOS

SA

A

P

0

SLAVE ADDRESS

COMMAND BYTE

ACKNOWLEDGE FROM MAX7300

R/W

ACKNOWLEDGE FROM MAX7300

D15 D14 D13 D12 D11 D10

D9

D8

COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION

Figure 7. Command Byte Received

SA

A

A

P

0

SLAVE ADDRESS

COMMAND BYTE

DATA BYTE

ACKNOWLEDGE FROM MAX7300

1 BYTE

AUTOINCREMENT MEMORY WORD ADDRESS

D15 D14

D13 D12

D11 D10

D9

D8

D1

D0

D3

D2

D5

D4

D7

D6

HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER

ACKNOWLEDGE FROM MAX7300

ACKNOWLEDGE FROM MAX7300

R/W

Figure 8. Command and Single Data Byte Received