XC164CS datasheet(34/71 Pages) INFINEON

34 / 71 page

XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

Figure 7

Block Diagram of GPT1

With its maximum resolution of 2 system clock cycles, the GPT2 module provides

precise event control and time measurement. It includes two timers (T5, T6) and a

capture/reload register (CAPREL). Both timers can be clocked with an input clock which

is derived from the CPU clock via a programmable prescaler or with external signals. The

count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal on a port pin (TxEUD).

Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,

which changes its state on each timer overflow/underflow.

The state of this latch may be used to clock timer T5, and/or it may be output on pin

T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the

CAPCOM1/2 timers, and to cause a reload from the CAPREL register.

The CAPREL register may capture the contents of timer T5 based on an external signal

transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared

Mo de

C ontro l

2 n : 1

SY S

2 n : 1

SY S

Mo de

C ontro l

G P T1 Tim e r T2

Reloa d

C apture

2 n : 1

SY S

Mo de

C ontro l

G P T1 Tim e r T4

Reloa d

C apture

G P T1 Tim e r T3

T3O T L

U/D

T2EU D

T2IN

T3IN

T3EU D

T4IN

T4EU D

Toggle FF

U/D

In te rru pt

R equest

(T 2 IR )

In te rru pt

R equest

(T 3 IR )

In te rru pt

R equest

(T 4 IR )

M c t04825_xc.v sd

T6 O U T

n = 2 … 12

XC164CS Scheda tecnica(PDF) 34 Page - Infineon Technologies AG

XC164CS Scheda tecnica(HTML) 34 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Scheda tecnica Scarica

Link URL