XC164CS datasheet(18/71 Pages) INFINEON

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XC164

Derivatives

Functional Description

Data Sheet

V2.1, 2003-06

Functional Description

The architecture of the XC164 combines advantages of RISC, CISC, and DSP

processors with an advanced peripheral subsystem in a very well-balanced way. In

addition, the on-chip memory blocks allow the design of compact systems-on-silicon with

maximum performance (computing, control, communication).

The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data

SRAM) and the set of generic peripherals are connected to the CPU via separate buses.

Another bus, the LXBus, connects additional on-chip resoures as well as external

resources (see Figure 3).

This bus structure enhances the overall system performance by enabling the concurrent

operation of several subsystems of the XC164.

The following block diagram gives an overview of the different on-chip components and

of the advanced, high bandwidth internal bus structure of the XC164.

Figure 3

Block Diagram

In terrup t B u s

XTAL

M C B 0 4323_x4.vs d

Osc / PLL

C lock G enera tion

RTC

WD T

GPT

SSC0

BR G e n

(S P I)

AS C1

BR G en

(U SAR T )

ADC

8/10-B it

12 /1 6

C hannels

CC2

CC 6

T1 2

T1 3

EBC

XBU S C o n tro l

Ex tern al Bu s

Con trol

ProgM em

Flash / R O M

128 K B ytes

P 2 0

Po rt 5

PSRAM

DPRAM

DS RA M

C 166SV2-C ore

CP U

AS C 0

BR G e n

(U SAR T )

SS C1

BR G e n

(SPI)

CC 1

Tw in

CAN

PO R T 1

PO R T 0

Po rt 3

Po rt 4

Po rt 9

Interrupt & PE C

P e ripheral D a ta Bus

OCDS

D ebug Support

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