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C161PI Scheda tecnica(PDF) 47 Page - Infineon Technologies AG |
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C161PI Scheda tecnica(HTML) 47 Page - Infineon Technologies AG |
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47 / 82 page  &3, Data Sheet 45 1999-07 AC Characteristics Definition of Internal Timing The internal operation of the C161PI is controlled by the internal CPU clock f CPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called “TCL” (see figure below). Figure 11 Generation Mechanisms for the CPU Clock The CPU clock signal I CPU can be generated from the oscillator clock signal IOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate I CPU. This influence must be regarded when calculating the timings for the C161PI. Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4. The used mechanism to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13 (P0H.7-5). The table below associates the combinations of these three bits with the respective clock generation mode. TCL TCL TCL TCL I&38 I26& I&38 I26& 3KDVH/RFNHG/RRS2SHUDWLRQ 'LUHFW&ORFN'ULYH TCL TCL I&38 I26& 3UHVFDOHU2SHUDWLRQ |
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