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C161PI Scheda tecnica(PDF) 30 Page - Infineon Technologies AG |
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C161PI Scheda tecnica(HTML) 30 Page - Infineon Technologies AG |
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30 / 82 page  &3, Data Sheet 28 1999-07 Parallel Ports The C161PI provides up to 76 IO lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The other IO ports operate in push/pull mode, except for the I²C interface pins which are open drain pins only. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A22/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output CLKOUT (or the programmable frequency output FOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. Port 6 provides the optional chip select signals and interface lines for the I²C module. The edge characteristics (transition time) of the C161PI’s port drivers can be selected via the Port Driver Control Register (PDCR). |
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