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C161PI Scheda tecnica(PDF) 48 Page - Infineon Technologies AG |
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C161PI Scheda tecnica(HTML) 48 Page - Infineon Technologies AG |
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48 / 82 page  &3, Data Sheet 46 1999-07 Prescaler Operation When pins P0.15-13 (P0H.7-5) equal 001 B during reset the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of I CPU is half the frequency of IOSC and the high and low time of ICPU (i.e. the duration of an individual TCL) is defined by the period of the input clock I OSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of I OSC for any TCL. Phase Locked Loop For all combinations of pins P0.15-13 (P0H.7-5) except for 001 B and 011B the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. I CPU = IOSC * F). With every F’th transition of IOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of I CPU is constantly adjusted so it is locked to I OSC. The slight variation causes a jitter of ICPU which also effects the duration of individual TCLs. Table 8 C161PI Clock Generation Modes P0.15-13 (P0H.7-5) CPU Frequency I CPU = IOSC * F External Clock Input Range 1) Notes 11 1 I OSC * 4 2.5 to 6.25 MHz Default configuration 110 I OSC * 3 3.33 to 8.33 MHz 101 I OSC * 2 5 to 12.5 MHz 100 I OSC * 5 2 to 5 MHz 011 I OSC * 1 1 to 25 MHz Direct drive 2) 010 I OSC * 1.5 6.66 to 16.6 MHz 001 I OSC / 2 2 to 50 MHz CPU clock via prescaler 000 I OSC * 2.5 4 to 10 MHz 1) The external clock input range refers to a CPU clock range of 10...25 MHz. 2) The maximum frequency depends on the duty cycle of the external clock signal. |
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