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MB9DF565MLE Scheda tecnica(PDF) 8 Page - SPANSION |
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MB9DF565MLE Scheda tecnica(HTML) 8 Page - SPANSION |
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8 / 109 page ![]() D at aS he e t May 15, 2015, MB9D560_DS708-00001-3v0-E 7 CONFIDENTIAL Function Description Low-voltage detection (LVD) − Select voltage monitor External low-voltage detection (5V power line monitor): 3.9V, 4.1V, 4.3V Internal low-voltage detection (1.2V power line monitor): 0.9V − Internal low-voltage detection: always valid − External low-voltage detection: valid/invalid set − External low-voltage detection: set threshold voltage independently on RUN / PSS − Output when low-voltage detection External low-voltage detection: reset or NMI Internal low-voltage detection: reset Main Flash memory (TCFLASH) − Cortex-R5F ATCM connection 1 Main Flash memory as CPU 1 unit − HPM connection with 64-bit AXI − Flash memory configuration Interleave with 64-bit Flash 2 units − 2 address areas TCM (read only) AXI (read / write) − ECC support (SEC-DED) − Parallel programming support − Flash security Work Flash memory (WorkFLASH) − 2 Work Flash memories 1 Work Flash memory as CPU 1 unit − ECC support (SEC-DED) − Parallel programming support − Flash security Main SRAM (TCRAM) − BTCM connection of Cortex-R5F 1 main SRAM as CPU 1 unit Interleave with 2 ports of B0TCM and B1TCM − ECC support (SEC-DED) BootROM − Size: 16K byte − Boot operation support − Serial writer program support DMA controller (DMAC) − 16 channels − Transfer mode Block transfer, Burst transfer − Addressing mode Fixed, increment − Priority between channels Fixed, Dynamic, Round robin Interrupt control (IRC) − Support normal interrupt (IRQ) and non-maskable interrupt (NMI) − Normal interrupt (IRQ) Use Interrupt Request (IRQ) of Cortex-R5F 512 channels 32 level for priority − Support low latency interrupt response from VIC port of Cortex-R5F − Non-maskable interrupt (NMI) Use fast interrupt request (FIQ) of Cortex-R5F 32 channels 16 level for priority − Support software interrupt generation |
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