MB9DF565MLE datasheet(88/109 Pages) SPANSION

88 / 109 page

D at aS he e t

May 15, 2015, MB9D560_DS708-00001-3v0-E

CONFIDENTIAL

(5-1-7) When the Serial Chip Select is Used (SCSCR:CSEN=1)

− Serial clock output signal detect level "H"(SMR, SCSFR:SCINV=0)

− Serial Chip select inactive level "L"(SCSCR, SCSFR:CSLVL=0)

(TA: Recommended operating conditions, VCC=5.0V±0.5V, VDD=1.2V±0.1V, VSS=AVSS=RVSS=0.0V)

Parameter

Symbol

Pin Name

Conditions

Value

Unit

Remarks

Min

Max

SCS↑→SCK↓

setup time

tCSSI

SCK4,

SCS40 to SCS43

Master mode

(CL=50pF,

IOL=-2mA, IOH=2mA),

(CL=20pF,

IOL=-1mA, IOH=1mA)

tCSSU*1-50

SCK↑→SCS↓

hold time

tCSHI

tCSHD*2+0

SCS deselect time

tCSDI

SCS40 to SCS43

tCSDS*3-50

+5tCLK_PERI1

SCS↑→SCK↓

setup time

tCSSE

SCK4,

SCS40 to SCS43

Slave mode

(CL=50pF,

IOL=-2mA, IOH=2mA),

(CL=20pF,

IOL=-1mA, IOH=1mA)

3tCLK_PERI1+30

SCK↑→SCS↓

hold time

tCSHE

SCS deselect time

tCSDE

SCS40 to SCS43

3tCLK_PERI1+30

SCS↑→SOT

delay time

tDSE

SCS40 to SCS43,

SOT4

SCS↓→SOT

delay time

tDEE

SCK↓→SCS↑

clock switch time

tSCC

SCK4,

SCS40 to SCS43

Master mode,

round operation

(CL=50pF,

IOL=-2mA,IOH=2mA),

(CL=20pF,

IOL=-1mA, IOH=1mA)

3tCLK_PERI1+0

3tCLK_PERI1

+50

Transfer speed

CL=50pF,

IOL=-2mA, IOH=2mA

Mbps

CL=20pF,

IOL=-1mA, IOH=1mA

Mbps

*1: tCSSU =SCSTR:CSSU[7:0]  serial chip select timing operation clock

*2: tCSHD=SCSTR:CSHD[7:0]  serial chip select timing operation clock

*3: tCSDS=SCSTR:CSDS[15:0]  serial chip select timing operation clock

For details of *1, *2 and *3 above, see Hardware Manual.

Notes:

−

This is the AC characteristic in CLK synchronized mode.

−

CL is the load capacitance applied to pins during testing.

−

The maximum baud rate is limited by the internal operation clock used and other parameters.

See Hardware Manual for details.

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