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HT48R50A Scheda tecnica(PDF) 8 Page - Holtek Semiconductor Inc |
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HT48R50A Scheda tecnica(HTML) 8 Page - Holtek Semiconductor Inc |
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8 / 46 page ![]() Functional Description HT48R50A-1 Rev. 1.10 8 July 2, 2001 Execution flow The system clock for the microcontroller is de- rived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an in- struction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to ef- fectively execute in a cycle. If an instruction changes the program counter, two cycles are re- quired to complete the instruction. Program counter - PC The program counter (PC) controls the se- quence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word contain- ing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subrou- tine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the pro- gram transfer by loading the address corre- sponding to each instruction. The conditional skip is activated by instruc- tions. Once the condition is met, the next in- struction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper in- struction. Otherwise proceed to the next in- struction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the cur- rent program ROM page. When a control transfer takes place, an addi- tional dummy cycle is required. Program memory - ROM The program memory is used to store the pro- gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096´15 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: · Location 000H This area is reserved for program initializa- tion. After chip reset, the program always be- gins execution at location 000H. T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 F e tc h IN S T ( P C ) E x ec ut e I N S T ( P C - 1 ) F e tc h IN S T ( P C + 1 ) E x ec ut e I N S T ( P C ) F e tc h IN S T ( P C + 2 ) E x ec ut e I N S T ( P C + 1 ) PC PC + 1 PC + 2 S yst e m C l o ck OS C 2 ( R C o nl y ) PC Execution flow |
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