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HT48R50A Scheda tecnica(PDF) 20 Page - Holtek Semiconductor Inc

Il numero della parte HT48R50A
Spiegazioni elettronici  8-Bit Microcontroller
PDF  46 Pages
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Produttore elettronici  HOLTEK [Holtek Semiconductor Inc]
Homepage  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT48R50A Scheda tecnica(HTML) 20 Page - Holtek Semiconductor Inc

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HT48R50A-1
Rev. 1.10
20
July 2, 2001
0. The internal clock source can be selected as
coming from (can always be optioned) or fRTC
(enabled only system oscillator in the Int.
RC+RTC mode) by ROM code option. The exter-
nal clock input allows the user to count external
events, measure time intervals or pulse widths,
or to generate an accurate time base and PFD
signals.
Using the internal clock sources, there are 2
reference time-bases for Timer/Event Counter
1. The internal clock source can be selected as
coming from fSYS/4 (can always be optioned) or
fRTC (enable only the system oscillator in the
Int. RC+RTC mode) by ROM code option. The
external clock input allows the user to count ex-
ternal events, measure time intervals or pulse
widths or to generate an accurate time base.
There are 2 registers related to the Timer/Event
Counter 0; TMR0 ([0DH]), TMR0C ([0EH]). Two
physical registers are mapped to TMR0 location;
writing TMR0 makes the starting value be placed
intheTimer/EventCounter0preloadregisterand
reading TMR0 gets the contents of the
Timer/Event Counter 0. The TMR0C is a
timer/event counter control register, which de-
finessomeoptions.
There are 3 registers related to Timer/Event
Counter 1; TMR1H (0FH), TMR1L (10H),
TMR1C (11H). Writing TMR1L will only put
the written data to an internal lower-order byte
buffer (8 bits) and writing TMR1H will transfer
the specified data and the contents of the
lower-order byte buffer to TMR1H and TMR1L
preload registers, respectively. The
Timer/Event Counter 1 preload register is
changed by each writing TMR1H operations.
Reading TMR1H will latch the contents of
TMR1H and TMR1L counters to the destina-
tion and the lower-order byte buffer, respec-
tively. Reading the TMR1L will read the
contents of the lower-order byte buffer. The
TMR1C is the Timer/Event Counter 1 control
TM 1
TM 0
TM R 0
TE
TM 1
TM 0
TO N
P u l s e W i dt h
M eas ur e m ent
M ode C o nt r ol
T i m e r / E v ent C ount e r 0
P r el oad R e gi s t er
Ti m e r / E v e nt
C ount e r 0
Da t a B u s
R e l oad
O v er f l ow
t o I nt e r r up t
1/ 2
BZ
BZ
8- s t age P r e s c a l e r
8- 1 M U X
f SY S
f IN T
PS C 2 ~ P SC 0
M
U
X
f RT C
R O M C ode O p t i on
( 1 /2 ~ 1 /2 5 6 )
Timer/Event Counter 0
TM 1
TM 0
TM R 1
TE
TM 1
TM 0
TO N
P u l s e W i dt h
M eas ur e m ent
M ode C o nt r ol
16 B i t s
T i m e r / E v ent C ount e r
P r el oad R e gi s t er
Da t a B u s
R e l oad
O v er f l ow
to I nte r r u p t
f SY S/ 4
M
U
X
f RT C
R O M C ode O p t i on
16 B i t s
T i m e r / E v ent C ount e r
( T M R 1H / T M R 1L)
Low B y t e
Bu f f e r
Timer/Event Counter 1



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