HT48R50A datasheet(17/46 Pages) HOLTEK

Il numero della parte	HT48R50A

Spiegazioni elettronici	8-Bit Microcontroller

PDF	46 Pages

Scroll/Zoom	100%

Produttore elettronici	HOLTEK [Holtek Semiconductor Inc]

Homepage	http://www.holtek.com

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17 / 46 page

HT48R50A-1

Rev. 1.10

July 2, 2001

To guarantee that the system oscillator is

started and stabilized, the SST (System

Start-up Timer) provides an extra-delay of

1024 system clock pulses when the system reset

(power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is

added during the reset period. Any wake-up

from HALT will enable the SST delay.

The functional unit chip reset status are shown

below.

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/event

Counter

Off

Input/output

Ports

Input mode

Points to the top of the stack

V DD

RE S

Reset circuit

W a r m R es et

WD T

HA L T

Co l d

Re s e t

RE S

S y s t em R e s et

SS T

10- bi t R i ppl e

C ount e r

OS C 1

Reset configuration

t SS T

RE S

VD D

S S T T i m e - out

C h i p R es et

Reset timing chart

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