ADAU1772BCPZ-R7 datasheet(43/117 Pages) AD

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ADAU1772

Data Sheet

Rev. C | Page 42 of 116

I2C Read and Write Operations

Figure 85 shows the timing of a single-word write operation.

Every ninth clock pulse, the ADAU1772 issues an acknowledge

by pulling SDA low.

Figure 86 shows the timing of a burst mode write sequence. This

figure shows an example where the target destination words are

two bytes, such as the program memory. The ADAU1772 knows

to increment its subaddress register every two bytes because the

requested subaddress corresponds to a register or memory area

with a 2-byte word length.

The timing of a single-word read operation is shown in Figure 87.

Note that the first R/W bit is 0, indicating a write operation. This

is because the subaddress still needs to be written to set up the

internal address. After the ADAU1772 acknowledges the receipt

of the subaddress, the master must issue a repeated start command

followed by the chip address byte with the R/W set to 1 (read).

This causes the ADAU1772 SDA to reverse and begin driving data

back to the master. The master then responds every ninth pulse

with an acknowledge pulse to the ADAU1772.

Figure 88 shows the timing of a burst mode read sequence. This

figure shows an example where the target read words are two

bytes. The ADAU1772 increments its subaddress every two bytes

because the requested subaddress corresponds to a register or

memory area with word lengths of two bytes. Other address

ranges may have a variety of word lengths, ranging from one to

four bytes. The ADAU1772 always decodes the subaddress and

sets the auto-increment circuit so that the address increments

after the appropriate number of bytes.

Figure 85 to Figure 88 use the following abbreviations:

S = start bit

P = stop bit

AM = acknowledge by master

AS = acknowledge by slave

Figure 85. Single-Word I2C Write Format

Figure 86. Burst Mode I2C Write Format

Figure 87. Single-Word I2C Read Format

Figure 88. Burst Mode I2C Read Format

I2C ADDRESS,

R/W = 0

SUBADDRESS HIGH

SUBADDRESS LOW

DATA BYTE 1

DATA BYTE 2

...

DATA BYTE N

...

I2C ADDRESS,

R/W = 0

SUBADDRESS

HIGH

SUBADDRESS

LOW

DATAWORD 1,

BYTE 1

DATAWORD 1,

BYTE 2

DATAWORD 2,

BYTE 1

DATAWORD 2,

BYTE 2

DATA BYTE 1

DATA BYTE 2

...

DATA BYTE N

I2C ADDRESS,

R/W = 0

SUBADDRESS

HIGH

SUBADDRESS

LOW

I2C ADDRESS,

R/W = 1

...

DATAWORD 1,

BYTE 1

DATAWORD 1,

BYTE 2

I2C ADDRESS,

R/W = 0

SUBADDRESS

HIGH

SUBADDRESS

LOW

I2C ADDRESS,

R/W = 1

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