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ADAU1772BCPZ-R7 Scheda tecnica(PDF) 60 Page - Analog Devices

Il numero della parte ADAU1772BCPZ-R7
Spiegazioni elettronici  Four ADC, Two DAC Low Power Codec
PDF  117 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADAU1772BCPZ-R7 Scheda tecnica(HTML) 60 Page - Analog Devices

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Data Sheet
ADAU1772
Rev. C | Page 59 of 116
FILTER ENGINE AND LIMITER CONTROL REGISTER
Address: 0x000B, Reset: 0x03, Name: CORE_ENABLE
Disabling the limiter only disables the attack operation. The decay operation is always active, so a limiter can be safely disabled while it
performs gain adjustments.
Table 40. Bit Descriptions for CORE_ENABLE
Bits
Bit Name
Settings
Description
Reset
Access
1
LIM_EN
Limiter enable. When the limiter function is disabled, a fixed max gain
setting is applied to instructions using the limiters.
0x1
RW
0
Disabled
1
Enabled
0
DSP_CLK_EN
Enable the clock to the core. Directly controls the clock to the core. It should
be set to 0 when the chip is used in a codec-only configuration, in which the
core is not used. Writing to any of the biquad coefficient registers (Parameter
Memory Address 0x0E0 to Address 0x2BF) is blocked until this bit is 1. This
bit should not be used to start or stop the core while it is running, because
it would immediately start or stop the core clock and not allow the program
to finish. Instead, use CORE_RUN in Register CORE_CONTROL to start or
stop the core.
0x1
RW
0
Core clock disabled
1
Core clock enabled



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