ADAU1772BCPZ-R7 datasheet(17/117 Pages) AD

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ADAU1772

Data Sheet

Rev. C | Page 16 of 116

Pin No.

Mnemonic

Type1

Description

AIN1REF

A_IN

ADC1 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.

AIN1

A_IN

ADC1 Input.

AIN2REF

A_IN

ADC2 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.

AIN2

A_IN

ADC2 Input.

AIN3REF

A_IN

ADC3 Input Reference. This reference pin should be ac-coupled to ground with a 10 µF capacitor.

AIN3

A_IN

ADC3 Input.

AVDD

PWR

1.8 V to 3.3 V Analog Supply. This pin should be decoupled to AGND with a 0.1 μF capacitor.

AGND

PWR

Analog Ground.

HPOUTLN/LOUTLN

A_OUT

Left Headphone Inverted (HPOUTLN).

Line Output Inverted (LOUTLN).

HPOUTLP/LOUTLP

A_OUT

Left Headphone Noninverted (HPOUTLP).

Line Output Noninverted, Single-Ended Line Output (LOUTLP).

AGND

PWR

Headphone Amplifier Ground.

AVDD

PWR

Headphone Amplifier Power, 1.8 V to 3.3 V Analog Supply. This pin should be decoupled to AGND

with a 0.1 μF capacitor. The PCB trace to this pin should be wider to supply the higher current necessary

for driving the headphone outputs.

HPOUTRN/LOUTRN

A_OUT

Right Headphone Inverted (HPOUTRN).

Line Output Inverted (LOUTRN).

HPOUTRP/LOUTRP

A_OUT

Right Headphone Noninverted (HPOUTRP).

Line Output Noninverted, Single-Ended Line Output (LOUTRP).

D_IN

Active Low Power-Down. All digital and analog circuits are powered down. There is an internal

pull-down resistor on this pin; therefore, the ADAU1772 is held in power-down mode if its input

signal is floating while power is applied to the supply pins.

REG_OUT

A_OUT

Regulator Output Voltage. This pin should be connected to DVDD if the internal voltage regulator

is being used to generate DVDD voltage.

DVDD

PWR

Digital Core Supply. The digital supply can be generated from an on-board regulator or supplied

directly from an external supply. In each case, DVDD should be decoupled to DGND with a 0.1 μF

capacitor.

DGND

PWR

Digital Ground. The AGND and DGND pins can be tied directly together in a common ground plane.

LRCLK/MP3

D_IO

Serial Data Port Frame Clock (LRCLK).

General-Purpose Input (MP3).

BCLK/MP2

D_IO

Serial Data Port Bit Clock (BCLK).

General-Purpose Input (MP2).

DAC_SDATA/MP0

D_IO

DAC Serial Input Data (DAC_SDATA).

General-Purpose Input (MP0).

ADC_SDATA0/PDMOUT/MP1

D_IO

ADC Serial Data Output 0 (ADC_SDATA0).

Stereo PDM Output to Drive a High Efficiency Class-D Amplifier (PDMOUT).

General-Purpose Input (MP1).

ADC_SDATA1/CLKOUT/MP6

D_IO

Serial Data Output 1 (ADC_SDATA1).

Master Clock Output/Clock for the Digital Microphone Input and PDM Output (CLKOUT).

General-Purpose Input (MP6).

DMIC2_3/MP5

D_IN

Digital Microphone Stereo Input 2 and Digital Microphone Stereo Input 3 (DMIC2_3).

General-Purpose Input (MP5).

DMIC0_1/MP4

D_IN

Digital Microphone Stereo Input 0 and Digital Microphone Stereo Input 1 (DMIC0_1).

General-Purpose Input (MP4).

XTALO

A_OUT

Crystal Clock Output. This pin is the output of the crystal amplifier and should not be used to

provide a clock to other ICs in the system. If a master clock output is needed, use CLKOUT (Pin 35).

XTALI/MCLKIN

D_IN

Crystal Clock Input (XTALI).

Master Clock Input (MCLKIN)

IOVDD

PWR

Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD, and this

sets the highest input voltage that should be seen on the digital input pins. The current draw of

this pin is variable because it is dependent on the loads of the digital outputs. IOVDD should be

decoupled to DGND with a 0.1 μF capacitor.

Exposed Pad. The exposed pad is connected internally to the ADAU1772 grounds. For increased

reliability of the solder joints and maximum thermal capability, it is recommended that the pad be

soldered to the ground plane. See the Exposed Pad PCB Design section for more information.

D_IO = digital input/output, D_IN = digital input, A_OUT = analog output, A_IN = analog input, PWR = power, A_IN = analog input.

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