HM25Q40C datasheet(42/62 Pages) HMSEMI

42 / 62 page

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except

that data is output on two pins, DO and DI, instead of just DO. This allows data to be transferred from the

ZB25VQ40/20 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for

quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to

RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest

possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”

clocks after the 24-bit address as shown in Figure 7.15. The dummy clocks allow the device's internal circuits

additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”.

However, the DI pin should be high-impedance prior to the falling edge of the first data out clock.

Figure 7.15 Fast Read Dual Output Instruction Sequence Diagram

7.3.4 Fast Read Quad Output (6Bh)

The Fast Read Quad Output (6Bh) instruction is similar to the Fast Dual Output (3Bh) instruction except

that data is output on four pins, IO0, IO1, IO2 and IO3. A Quad enable of status Register-2 must be executed

before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1).

The Fast Read Quad Output Instruction allows data to be transferred from ZB25VQ40/20 at four times the

rate of standard SPI devices.

The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC

Electrical Characteristics). This is accomplished by adding "dummy" clocks after the 24-bit address as shown

in Figure 7.16. The input data during the dummy clocks is "don't care". However, the IO pins should be

high-impedance prior to the falling edge of the first data out clock.

Figure 7.16 Fast Read Quad Output Instruction

7.3.5 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO

pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input

the Address bits (A23-0) two bits per dock. This reduced instruction overhead may allow for code execution

(XIP) directly from the Dual SPI in some applications.

Fast Read Dual I/O with "Continuous Read Mode"

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the

HM25Q40A

HM25Q40C Scheda tecnica(PDF) 42 Page - Shenzhen Huazhimei Semiconductor Co., Ltd