HM25Q40C datasheet(37/62 Pages) HMSEMI

37 / 62 page

While the Write Status Register cycle is in progress, the Read Status Register instruction may still be

accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and

a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register

cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.

During volatile Status Register write operation (50h combined with 01h/31h/11h), after CS# is driven high,

the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC

Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program

the Status Register-1, the Status Register-2 will not be affected.

Figure 7.5 Write Status Register Instruction

7.2 Program and Erase Commands

7.2.1 Page Program (PP) (02h)

The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to

all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the

Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the

CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one

data byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is

being sent to the device. The Page Program instruction sequence is shown in Figure 7.6.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)

should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page

length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial

page) can be programmed without having any effect on other bytes within the same page. One condition to

perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more

than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite

previously sent data.

As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last

byte has been latched. If this is not done the Page Program instruction will not be executed. After CS# is

driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC

Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still

be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and

becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the

Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The

Page Program instruction will not be executed if the addressed page is protected by the Block Protect (TB,

SEC, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).

Figure 7.6a Page Program Instruction

HM25Q40A

HM25Q40C Scheda tecnica(PDF) 37 Page - Shenzhen Huazhimei Semiconductor Co., Ltd