HM25Q40C datasheet(10/62 Pages) HMSEMI

10 / 62 page

Preliminary Datasheet

4.5. Write Protect (WP#) / IO2

The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, TB, SEC, CMP) bits and Status

The WP# function is not available when the Quad mode is enabled. The WP# function is replaced by IO2

for input and output during Quad mode for receiving addresses and data to be programmed (values are

latched on rising edge of the CLK signal) as well as shifting out data (on the falling edge of CLK).

4.6. HOLD (HOLD#) / IO3

The HOLD# pin allows the device to be paused while it is actively selected. When HRSW bit is ‘0’ (factory

default is ‘0’), the HOLD# pin is enabled. When HOLD# is brought low, while CS# is low, the DO pin will be at

high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high,

device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same

SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the

HOLD# pin function is not available since this pin is used for IO3.

4.7. RESET (RESET#) / IO3

The RESET# pin allows the device to be reset by the controller. When HRSW bit is ‘1’ (factory default is

‘0’), the RESET# pin is enabled. Drive RESET# low for a minimum period of ~1us (tRESET*) will interrupt any

on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP#

and/or HOLD#). The Hardware Reset function is only available for standard SPI and Dual SPI operation,

when QE=0, the IO3 pin can be configured either as a HOLD# pin or as a RESET# pin depending on Status

HM25Q40A

HM25Q40C Scheda tecnica(PDF) 10 Page - Shenzhen Huazhimei Semiconductor Co., Ltd