HM25Q40C datasheet(24/62 Pages) HMSEMI

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Preliminary Datasheet

Table 6.3 Status Register-3 (SR3)

Bits

Field

Function

Type

Default State

Description

HRSW(1)

HOLD# or

RESET#

function

Non-volatile

and Volatile

versions

When HRSW=0, the pin acts as HOLD#; when

HRSW=1, the pin acts as RESET#. HRSW

functions are only available when QE=0.

DRV1(1)

Output Driver

Strength

Volatile

The DRV1 & DRV0 bits are used to determine

the output driver strength for the Read

operations.

DRV0(1)

HFM

High

Frequency

Mode Enable

Bit

Non-volatile

and Volatile

versions

0 =High Frequency Mode Disabled

1 =High Frequency Mode Enabled

Reserve

Note:

1.Default state for these three bits could be modified. please contact sales.

6.2.1 BUSY

BUSY is a read only bit in the status register (SR1[0]) which is set to a “1” state when the device is

executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction.

During this time the device will ignore further instructions except for the Read Status Register instruction (see

tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has

completed, the BUSY bit will be cleared to a “0” state indicating the device is ready for further instructions.

6.2.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (SR1[1]) which is set to a 1 after

executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is written disabled.

A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page

Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

6.2.3 Block Protect Bits (BP2, BP1, BP0)

The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that

provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers

Command (see tW in Section 8.5). All, none or a portion of the memory array can be protected from Program

and Erase commands (see Section 6.4.2, Block Protection Maps). The factory default setting for the Block

Protection Bits is 0 (none of the array is protected.)

6.2.4 Top / Bottom Block Protect (TB)

The non-volatile Top / Bottom bit (TB SR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0)

protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 6.4.2, Block Protection

Maps. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers Command

depending on the state of the SRP0, SRP1 and WEL bits.

6.2.5 Sector / Block Protect (SEC)

The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)

protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) of the array as shown in Section 6.4.2, Block

HM25Q40A

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