JS28F256P30T85 datasheet(7/102 Pages) INTEL

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1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

1.0

Introduction

This document provides information about the Intel StrataFlash® Embedded Memory (P30) device

and describes its features, operation, and specifications.

1.1

Nomenclature

1.2

Acronyms

1.8 V :

VCC (core) voltage range of 1.7 V – 2.0 V

3.0 V :

VCCQ (I/O) voltage range of 1.7 V – 3.6 V

9.0 V :

VPP voltage range of 8.5 V – 9.5 V

Block :

A group of bits, bytes,1-Gbit P30 Family or words within the

flash memory array that erase simultaneously when the Erase

command is issued to the device. The 1-Gbit P30 Family has

two block sizes: 32-KByte and 128-KByte.

Main block :

An array block that is usually used to store code and/or data.

Main blocks are larger than parameter blocks.

Parameter block :

An array block that is usually used to store frequently changing

data or small system parameters that traditionally would be

stored in EEPROM.

Top parameter device :

A device with its parameter blocks located at the highest

physical address of its memory map.

Bottom parameter device :

A device with its parameter blocks located at the lowest

physical address of its memory map.

BEFP :

Buffer Enhanced Factory Programming

CUI :

Command User Interface

MLC :

Multi-Level Cell

OTP :

One-Time Programmable

PLR :

Protection Lock Register

PR :

Protection Register

RCR :

Read Configuration Register

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