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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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JS28F256P30T85 Scheda tecnica(PDF) 35 Page - Intel Corporation |
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JS28F256P30T85 Scheda tecnica(HTML) 35 Page - Intel Corporation |
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35 / 102 page  1-Gbit P30 Family Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 35 7.3 AC Read Specifications Table 16. AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2) Num Symbol Parameter Min Max Unit Notes Asynchronous Specifications R1 tAVAV Read cycle time 85 - ns R2 t AVQV Address to output valid - 85 ns R3 t ELQV CE# low to output valid - 85 ns R4 t GLQV OE# low to output valid - 25 ns 1,2 R5 tPHQV RST# high to output valid - 150 ns 1 R6 tELQX CE# low to output in low-Z 0 - ns 1,3 R7 tGLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 tEHQZ CE# high to output in high-Z - 24 ns 1,3 R9 tGHQZ OE# high to output in high-Z - 24 ns R10 tOH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 tEHEL CE# pulse width high 20 - ns 1 R12 tELTV CE# low to WAIT valid - 17 ns R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3 R15 tGLTV OE# low to WAIT valid - 17 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3 R17 tGHTZ OE# high to WAIT in high-Z - 20 ns Latching Specifications R101 tAVVH Address setup to ADV# high 10 - ns 1 R102 tELVH CE# low to ADV# high 10 - ns R103 tVLQV ADV# low to output valid - 85 ns R104 tVLVH ADV# pulse width low 10 - ns R105 tVHVL ADV# pulse width high 10 - ns R106 tVHAX Address hold from ADV# high 9 - ns 1,4 R108 tAPA Page address access - 25 ns 1 R111 tphvh RST# high to ADV# high 30 - ns Clock Specifications R200 fCLK CLK frequency - 40 MHz 1,3,6 R201 tCLK CLK period 25 - ns R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns Synchronous Specifications R301 tAVCH/L Address setup to CLK 9 - ns 1 R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 20 ns |
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