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R5F572TFGDFP Scheda tecnica(PDF) 120 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 120 Page - Renesas Technology Corp |
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120 / 176 page ![]() R01DS0331EJ0100 Rev.1.00 Page 120 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics 5.4.1 Reset Timing Figure 5.2 Reset Input Timing at Power-On Figure 5.3 Reset Input Timing Table 5.13 Reset Timing Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr Item Symbol Min. Typ. Max. Unit Test Conditions RES# pulse width Power-on tRESWP 2.0 — — ms Figure 5.2 Deep software standby mode tRESWD 0.6 — — Figure 5.3 Software standby mode tRESWS 0.3 — — Programming or erasure of the code flash memory, or programming, erasure or blank checking of the data flash memory tRESWF 200 — — μs Other than above tRESW 200 — — Waiting time after release from the RES# pin reset tRESWT 62 — 63 tLcyc Figure 5.2 Internal reset time (independent watchdog timer reset, watchdog timer reset, software reset) tRESW2 108 — 116 VCC RES# Internal reset signal (Low is valid) tRESWP tRESWT RES# Internal reset signal (Low is valid) tRESWD, tRESWS, tRESWF, tRESW tRESWT |
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