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R5F572TFGDFP Scheda tecnica(PDF) 121 Page - Renesas Technology Corp

Il numero della parte R5F572TFGDFP
Spiegazioni elettronici  Maximum operating frequency: 200 MHz Capable of 1160 CoreMark in operation at 200 MHz
PDF  176 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F572TFGDFP Scheda tecnica(HTML) 121 Page - Renesas Technology Corp

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R01DS0331EJ0100 Rev.1.00
Page 121 of 176
Feb 08, 2019
RX72T Group
5. Electrical Characteristics
5.4.2
Clock Timing
Figure 5.4
BCLK Pin Output Timing
Table 5.14
BCLK Pin Output Clock Timing (1)
Conditions: 4.5 V ≤ VCC ≤ 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
BCLK pin output cycle time
tBcyc
25
—
—
ns
Figure 5.4
BCLK pin output high pulse width
tCH
7.5
—
—
BCLK pin output low pulse width
tCL
7.5
—
—
BCLK pin output rising time
tCr
——
5
BCLK pin output falling time
tCf
——
5
Table 5.15
BCLK Pin Output Clock Timing (2)
Conditions: 2.7 V ≤ VCC < 4.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V,
Ta = Topr
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
BCLK pin output cycle time
tBcyc
31.25
—
—
ns
Figure 5.4
BCLK pin output high pulse width
tCH
10.625
—
—
BCLK pin output low pulse width
tCL
10.625
—
—
BCLK pin output rising time
tCr
——
5
BCLK pin output falling time
tCf
——
5
tCf
tCH
tBcyc
tCr
tCL
BCLK pin output
Test conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF
High-drive output is selected by the driving ability control register.



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