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R5F572TFGDFP Scheda tecnica(PDF) 136 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 136 Page - Renesas Technology Corp |
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136 / 176 page ![]() R01DS0331EJ0100 Rev.1.00 Page 136 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics 5.4.6 Timing of On-Chip Peripheral Modules Note 1. tPBcyc: PCLKB cycle Figure 5.23 I/O Port Input Timing Note 1. tPBcyc: PCLKB cycle Figure 5.24 TMR Clock Input Timing Table 5.26 I/O Port Timing Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item Symbol Min. Max. Unit*1 Test Conditions I/O ports Input data pulse width tPRW 1.5 — tPBcyc Figure 5.23 Table 5.27 TMR Timing Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V, VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr, ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65). Item Symbol Min. Max. Unit*1 Test Conditions TMR Timer clock pulse width Single-edge setting tTMCWH, tTMCWL 1.5 — tPBcyc Figure 5.24 Both-edge setting 2.5 — Port PCLKB tPRW PCLKB TMCI0 to TMCI7 tTMCWL tTMCWH |
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