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R5F572TFGDFP Scheda tecnica(PDF) 139 Page - Renesas Technology Corp |
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R5F572TFGDFP Scheda tecnica(HTML) 139 Page - Renesas Technology Corp |
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139 / 176 page ![]() R01DS0331EJ0100 Rev.1.00 Page 139 of 176 Feb 08, 2019 RX72T Group 5. Electrical Characteristics Figure 5.27 POE Input Timing Figure 5.28 Output Disable Time for POE in Response to Transition of the POEn# Signal Level Figure 5.29 Output Disable Time for POE in Response to the Simultaneous Conduction of Output Pins Figure 5.30 Output Disable Time for POE in Response to Detection of the Comparator Outputs POEn# input (n = 0, 4, 8 to 14) PCLKB tPOEW POEn# input (n = 0, 4, 8 to 14) MTU PWM output pins GPTW PWM output pins Outputs disabled tPOEW tPOEDI Outputs disabled Simultaneous active-level outputs detected*1 Note 1. When the active level is set to low. MTU PWM output pins GPTW PWM output pins tPOEDO COMPn level detection signal (n = 0 to 5) MTU PWM output pins GPTW PWM output pins Outputs disabled tPOEDC |
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