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R5F572TFGDFP Scheda tecnica(PDF) 137 Page - Renesas Technology Corp

Il numero della parte R5F572TFGDFP
Spiegazioni elettronici  Maximum operating frequency: 200 MHz Capable of 1160 CoreMark in operation at 200 MHz
PDF  176 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F572TFGDFP Scheda tecnica(HTML) 137 Page - Renesas Technology Corp

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R01DS0331EJ0100 Rev.1.00
Page 137 of 176
Feb 08, 2019
RX72T Group
5. Electrical Characteristics
Note 1. tPCcyc: PCLKC cycle
Figure 5.25
MTU Input Capture Input Timing
Figure 5.26
MTU Clock Input Timing
Table 5.28
MTU Timing
Conditions: VCC = 2.7 to 5.5 V, VCC_USB = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5V,
VSS = VSS_USB = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,
ICLK = 8 to 200 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, PCLKC = 8 to 200 MHz, BCLK = 8 to 60 MHz,
Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,
High-drive output is selected by the driving ability control register (other than for P53 to P55 and P60 to P65).
Item
Symbol
Min.
Max.
Unit*1
Test
Conditions
MTU
Input capture input pulse
width
Single-edge
setting
tMTICW
1.5
—
tPCcyc
Figure 5.25
Both-edge
setting
2.5
—
Timer clock pulse width
Single-edge
setting
tMTCKWH,
tMTCKWL
1.5
—
tPCcyc
Figure 5.26
Both-edge
setting
2.5
—
Phase counting
mode
2.5
—
Input capture
input
PCLKC
tMTICW
MTCLKA to
MTCLKD,
MTIOC1A
PCLKC
tMTCKWL
tMTCKWH



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