RTI-18
BIPHASE OUTPUTS
NAME
PIN NUMBER
DESCRIPTION
LCC
PGA
BIPHASE OUT A Z
28
K8
TO
--
Transmitter - Channel A, Zero Output. This
Manchester-encoded data output is connected
to the 1553 bus transmitter input. The output is
idle low.
BIPHASE OUT A O
27
L8
TO
--
Transmitter - Channel A, One Output. This
output is the complement of BIPHASE OUT
A Z. The output is idle low.
BIPHASE OUT B Z
30
L10
TO
--
Transmitter - Channel B, Zero Output. This
Manchester-encoded data output is connected
to the 1553 bus transmitter. The output is idle
low.
BIPHASE OUT B O
32
L11
TO
--
Transmitter - Channel B, One Output. This
output is the complement of BIPHASE OUT
B Z. The output is idle low.
MASTER RESET AND CLOCK
NAME
PIN NUMBER
DESCRIPTION
LCC
PGA
MRST
40
G10
TUI
AL
Master Reset. Initializes all internal functions of the
RTI. MRST must be asserted 500 nanoseconds
before normal RTI operation. (500ns minimum).
12MHz
35
K11
TI
--
12MHz Input Clock. This is the RTI system clock
that requires an accuracy greater than 0.01% with a
duty cycle from 50%
±10%.
2MHz
24
L7
TO
--
2MHz Clock Output. This is a 2MHz output gener-
ated by the 12MHz input clock. This clock is
stopped when MRST is low.
POWER AND GROUND
NAME
PIN NUMBER
DESCRIPTION
LCC
PGA
VDD
54
B10
PWR
--
+5VDC. Power supply must be +5VDC ±10%.
VSS
12
42
K2
F10
GND
GND
--
--
Ground reference. Zero VDC logic ground.
TYPE
ACTIVE
TYPE
ACTIVE
TYPE
ACTIVE
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