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RTI-24
DMARQ
MEMCK
RCS
RRD/RWR
DATA BUS
ADDR OUT BUS
t10a
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNITS
ADDR OUT valid to DMARQ active 3
DMARQ active to MEMCK active 2, 3
MEMCK active to RCS active 4
MEMCK inactive to RCS inactive 4
MEMCK active to RRD/RWR active
MEMCK inactive to RRD/RWR inactive
MEMCK pulse width 1, 2, 4
MEMCK active to DATA bus valid 4
MEMCK inactive to DATA bus high
impedance 3
883
992
0-
-67
-61
-61
-58
83
-
-
115
5
101
Notes:
1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.
2. The sum tb + te must not exceed 18.8ms.
3. Supplied as a design limit, but not guaranteed or tested.
4. Guaranteed by test.
Figure 10. RTI Memory Write
ns
ns
ns
ns
ns
ns
ns
ns
ns
t10a
t10b
t10e
t10c
t10h
t10f
t10d
t10i
t10g
t10b
t10c
t10d
t10e
t10f
t10g
t10h
t10i