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RTI-38
PACKAGE OUTLINE DRAWINGS
L
L
K
H
G
F
E
D
C
B
A
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11
Figure 26a. UT1553B RTI Pingrid Array Configuration
(Bottom View)
L
L
L
L
L
L
L
L
L1
L1
K
K
K
K
K
K
K
K
K
K1
K1
J
J
J
J1
J1
H
H
H1
H1
G
G
G1
G1
F
F
F1
F1
E
E
E1
E1
D
D
D1
D1
C
C
C1
C1
B
B
B
B
B
B
B
B
B
B1
B1
A
A
A
A
A
A
A
A
A
A1
A1
C
C
C
J
J
J
G
F
E
G
F
E
F1
ADDR OUT 5
F2
ADDR IN 7
F3
ADDR IN 5
F9
RCS
F10
VSS
F11
DMARQ
G1
ADDR IN 4
G2
ADDR OUT 4
G3
ADDR IN 3
G9
BIPHASE IN A Z
G10
MRST
G11
TIMERON
H1
ADDR OUT 3
H2
ADDR IN 2
H10
BIPHASE IN A O
H11
XMIT
C1
ADDR OUT 9
C2
ADDR OUT 10
C5
DATA I/O 6
C6
TA 0
C7
DATA I/O 10
C10
TALEN/PARITY
C11
CTRL
D1
ADDR OUT 8
D2
ADDR IN 8
D10
MES ERR
D11
MEMCK
E1
ADDR IN 6
E2
ADDR OUT 7
E3
ADDR OUT 6
E9
CS
E10
RD/WR
E11
RRD/RWR
A1
DATA I/O 0
A2
DATA I/O 2
A3
DATA I/O 3
A4
DATA I/O 5
A5
DATA I/O 8
A6
DATA I/O 9
A7
TA 1
A8
DATA I/O 12
A9
DATA I/O 13
A10
DATA I/O 14
A11
DATA I/O 15
B1
ADDR IN 9
B2
ADDR IN 10
B3
DATA I/O 1
B4
DATA I/O 4
B5
DATA I/O 7
B6
DATA I/O 11
B7
TA 2
B8
TA 3
B9
TA 4
B10
VDD
B11
RCV
J1
ADDR OUT 2
J2
ADDR OUT 1
J5
MCSA 3
J6
COMSTR
J7
STATUS
J10
BIPHASE IN B Z
J11
BRDCST
K1
ADDR IN 1
K2
VSS
K3
ADDR IN 0
K4
MCSA 1
K5
MCSA 4
K6
MC/SA
K7
BCEN
K8
BIPHASE OUT A Z
K9
EXT TST CH SEl A/B
K10
BIPHASE IN B O
K11
12MHz
L1
ADDR OUT 0
L2
MCSA 0
L3
ADOEN
L4
MCSA 2
L5
ILL COMM
L6
CH A/B
L7
2MHz
L8
BIPHASE OUT A
L9
EXT TEST
L10
BIPHASE OUT B
L11
BIPHASE OUT B
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