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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

Bit

Interrupt Source

Conditions

INT_SWAP

Display list swap occurred

INT_TOUCH

touch detected

INT_TAG

Touch-screen tag value change

INT_SOUND

Sound effect ended

INT_PLAYBACK

Audio playback ended

INT_CMDEMPTY

Command FIFO empty

INT_CMDFLAG

Command FIFO flag

INT_CONV_COMPLETE Touch-screen conversions completed

INT_UNDERRUN

Graphics pipeline underrun

Table 4-6 Interrupt Flags bit assignment

4.2 System Clock

4.2.1

Clock Source

The BT817/8 supports external 12MHz crystal as clock source for system clock and RGB interface pixel

clock.

Figure 4-4 shows the pin connections for the crystal.

Figure 4-4 Crystal Oscillator Connection

4.2.2

Phase Locked Loop

There are 2 PLLs inside the chip, system PLL(PLL1) and PCLK PLL(PLL2).

The system PLL takes an input clock from the oscillator, and generates clocks to all internal circuits,

including the graphics engine, audio engine and touch engine.

The PCLK PLL (PLL2) takes an input clock from the oscillator, and generates clocks for RGB interface

when configured in Exsync mode.

4.2.3

Clock Enable

At power-on the BT817/8 is in sleep mode. The system clock will be enabled when the following step is

executed:



Host sends a “CLKEXT” command



Host sends an “ACTIVE” command

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