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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

4.9.3.1

ACTIVE state

In ACTIVE state, the BT817/8 is in normal operation. The clock oscillator and PLL are functioning. The

system clock applied to the BT817/8 core engines is enabled.

4.9.3.2

STANDBY state

In STANDBY state, the clock oscillator and PLL remain functioning; the system clock applied to the

BT817/8 core engines is disabled. All register contents are retained.

4.9.3.3

SLEEP state

In SLEEP state, the clock oscillator, PLL and system clock applied to the BT817/8 core engines are

disabled. All register contents are retained.

4.9.3.4

POWERDOWN state

In POWERDOWN state, the clock oscillator, the PLL and the system clock applied to the BT817/8 core

is disabled. The core engines are powered down while the SPI interface for host commands remains

functional. All register contents are lost and reset to default when the chip is next switched on. The

internal regulator remains on.

4.9.3.5

Wake up to ACTIVE from other power states

When in the POWERDOWN state, if the device enters this state via an SPI command, then only the SPI

ACTIVE command will bring the device back to the ACTIVE state, provided PD_N pin is also high.

However, if PD_N is used instead, then making PD_N high followed by a SPI ACTIVE command will

wake up the device. Upon exiting this state, the device will perform a global reset, and will go through

the same power up sequence. All settings from SPI commands will be reset except those that pertain

to pin states during power down. The clock enable sequence mentioned in section 4.2.3 shall be

executed to properly select and enable the system clock.

From the SLEEP state, the host MPU sends an SPI ACTIVE command to wake the BT817/8 into the

ACTIVE state. The host needs to wait for at least 20ms before accessing any registers or commands.

This is to guarantee the clock oscillator and PLL are up and stable.

From the STANDBY state, the host MPU sends SPI ACTIVE command to wake the BT817/8

into the ACTIVE state. The host can immediately access any register or command.

4.9.4

Reset and Boot-up Sequence

There are a few hardware and software reset events which can be triggered to reset the BT817/8.

Hardware reset events:



Power-on-Reset(POR)



A low pulse of 5ms on PD_N pin (applicable when chip is in ACTIVE or STANDBY state)

Software reset events:



SPI command RST_PULSE



SPI command to enter POWERDOWN then wakeup

After reset the BT817/8 will be in the SLEEP state. Upon receiving the SPI ACTIVE command (or

CLKEXT followed by SPI ACTIVE command if external clock source is used), the clock oscillator and

PLL will start up. Once the clock is stable, the chip will check and repair its internal RAM, running the

configuration and then entering into normal operations. The boot-up may take up to 300ms to

complete. During boot up process, software should not access BT817/8 register or RAM except reading

REG_ID and REG_CPURESET.

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