BT817Q-R datasheet(13/59 Pages) BRIDGETEK

13 / 59 page

BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

Figure 4-3 Quad SPI Interface connection

4.1.2

Serial Data Protocol

The BT817/8 appears to the host MPU/MCU as a memory-mapped SPI device. The host communicates

with the BT817/8 using reads and writes to a large (4 megabyte) address space. Within this address

space are dedicated areas for graphics, audio and touch control. Refer to section 5 for the detailed

memory map. The host reads and writes the BT817/8 address space using SPI transactions. These

transactions are memory read, memory write and command write. Serial data is sent by the most

significant bit first. Each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s

no limit on data length within one transaction, as long as the memory address is continuous.

4.1.3

Host Memory Read

For SPI memory read transactions, the host sends two zero bits, followed by the 22-bit address. This is

followed by a dummy byte. After the dummy byte, the BT817/8 responds to each host byte with read

data bytes.

Byte n

Table 4-2 Host Memory Read Transaction

Address [21:16]

Address [15:8]

Address [7:0]

Dummy byte

Byte 0

GND

SCLK

MISO

IO2

SS#

PD#

INT#

SCK

MISO

IO2

CS_N

PD_N

INT_N

BT817/8

1.8-3.3V

VCCIO1

3.3V

VCC

4.7k

MPU/MCU

MOSI

IO3

MOSI

IO3

Read Data

Write

Address

BT817Q-R Scheda tecnica(PDF) 13 Page - Bridgetek Pte Ltd.

BT817Q-R Scheda tecnica(HTML) 13 Page - Bridgetek Pte Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Scheda tecnica Scarica

Link URL