BT817Q-R datasheet(41/59 Pages) BRIDGETEK

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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

Address

(hex)

Bit

Reset

value

Description

302054h

REG_DLSWAP

2 r/w

0 Display list swap control

302058h

REG_ROTATE

3 r/w

0 Screen rotation control. Allow

normal/mirrored/inverted for

landscape or portrait orientation.

30205Ch

REG_OUTBITS

9 r/w

0 Output bit resolution, 3 register

bits each for R/G/B data pins. 0

indicates 8 bits, 1-7 indicates 1-7

bits respectively.

302060h

REG_DITHER

1 r/w

1 Output dither enable

302064h

REG_SWIZZLE

4 r/w

0 Output RGB signal swizzle

302068h

REG_CSPREAD

1 r/w

1 Output clock spreading enable

30206Ch

REG_PCLK_POL

1 r/w

0 PCLK polarity:

0: output on PCLK rising edge,

1: output on PCLK falling edge

302070h

REG_PCLK

8 r/w

0 PCLK frequency divider

0: disable

1: EXTSYNC mode

2-255: divider from system clock

302074h

REG_TAG_X

11 r/w

0 Tag query X coordinate

302078h

REG_TAG_Y

11 r/w

0 Tag query Y coordinate

30207Ch

REG_TAG

8 r/o

0 Tag query result

302080h

REG_VOL_PB

8 r/w

FFh Volume for playback

302084h

REG_VOL_SOUND

8 r/w

FFh Volume for synthesizer sound

302088h

REG_SOUND

16 r/w

0 Sound effect select

30208Ch

REG_PLAY

1 r/w

0h Start effect playback

302090h

REG_GPIO_DIR

8 r/w

80h Legacy GPIO pin direction,

0 = input , 1 = output

302094h

REG_GPIO

8 r/w

00h Legacy GPIO read/write

302098h

REG_GPIOX_DIR

16 r/w

8000h Extended GPIO pin direction,

0 = input , 1 = output

30209Ch

REG_GPIOX

16 r/w

0080h Extended GPIO read/write

3020A0h

3020A4h

Reserved

- Reserved

3020A8h

REG_INT_FLAGS

9 r/o

000h Interrupt flags, clear by read

3020Ach

REG_INT_EN

1 r/w

0 Global interrupt enable, 1=enable

3020B0h

REG_INT_MASK

9 r/w

1FFh Individual interrupt enable,

1=enable. Firmware sets to ffh at

boot.

3020B4h

REG_PLAYBACK_START

20 r/w

0 Audio playback RAM start address

3020B8h

REG_PLAYBACK_LENGTH

20 r/w

0 Audio playback sample length

(bytes)

3020BCh

REG_PLAYBACK_READPTR

20 r/o

- Audio playback current read

pointer

3020C0h

REG_PLAYBACK_FREQ

16 r/w

8000 Audio playback sampling

frequency (Hz)

3020C4h

REG_PLAYBACK_FORMAT

2 r/w

0 Audio playback format

3020C8h

REG_PLAYBACK_LOOP

1 r/w

0 Audio playback loop enable

3020CCh

REG_PLAYBACK_PLAY

1 r/w

0 Start audio playback

3020D0h

REG_PWM_HZ

14 r/w

250 BACKLIGHT PWM output

frequency (Hz)

3020D4h

REG_PWM_DUTY

8 r/w

128 BACKLIGHT PWM output duty

cycle 0=0%, 128=100%

3020D8h

REG_MACRO_0

32 r/w

0 Display list macro command 0

3020DCh

REG_MACRO_1

32 r/w

0 Display list macro command 1

3020E0h

–

3020F4h

Reserved

- -

- Reserved

3020F8h

REG_CMD_READ

12 r/w

0 Command buffer read pointer

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