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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

1st Byte

2nd byte

3rd byte

Command

Description

18h

SPIM_IO2

19h

SPIM_IO3

Others

Reserved

Note: GPIO0 shares the same pin as SPI

IO2 and GPIO1 with SPI IO3. When SPI

is set in Quad mode, IO2 and IO3 will

inherit the drive strength set in GROUP

13h; otherwise GPIO0 and GPIO1 will

inherit the drive strength from GROUP

00h and 01h respectively.

01110001b

00000000b

71h

PIN_PD_STA

During power down, I/O pins will have

different state as compared to normal

operating mode. Please refer to Table

4-23 for their default power down state.

These settings will only be effective

during power down and will not affect

normal operations. Also note that these

configuration bits are sticky and, unlike

other configuration bits, will not reset to

default values upon exiting power down.

Only POR will reset them.

Byte2 determines which pin and the

setting are to be updated.

Byte2[1:0] determine the pin state.

Byte2 [1:0]

Pin Setting

Float

Pull-Down

Pull-Up

Reserved

Byte2[7:2]

determine

which

pin/pin

group to set.

Please refer to the table in command

PINDRIVE entry.

Table 4-5 Host Command List

Note: Any command code not specified is reserved and should not be used by the software

4.1.6

Interrupts

The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tri-state (pulled to

high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when any of the interrupt

flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Writing a ‘1’ in any bit of

REG_INT_MASK will enable the corresponding interrupt. Each bit in REG_INT_FLAGS is set by a

corresponding interrupt source. REG_INT_FLAGS is readable by the host at any time, and clears when

read.

The INT_N pin is open-drain (OD) output by default. It can be configured to push-pull output by register

REG_GPIOX.

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