BT818Q-R datasheet(24/59 Pages) BRIDGETEK

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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

Figure 4-5 Flash Interface States

The register REG_FLASH_STATE indicates the state of the flash subsystem. At boot the flash state is

FLASH_STATE_INIT. After detection has completed flash is in state FLASH_STATE_DETACHED or

FLASH_STATE_BASIC, depending on whether an attached flash device was detected.

If no device is detected, then all SPIM signals are driven to low or high, except SPIM_MISO which is Hi-

When the host MCU calls CMD_FLASHFAST, the flash system attempts to go to full-speed mode, setting

state to FLASH_STATE_FULL (Note: the 4K byte flash blob file needs to program to the flash before the

flash can enter full-speed mode).

At any time the user can call CMD_FLASHDETACH in order to disable flash communications. In the

detached state, commands CMD_FLASHSPIDESEL, CMD_FLASHSPITX and CMD_FLASHSPIRX can be

used to control the SPI bus.

If detached, the host MCU can call CMD_FLASHATTACH to re-establish communication with the flash

device.

Direct rendering of bitmaps from flash is only possible in FLASH_STATE_FULL. After modifying the

contents of flash, the MCU should clear the on-chip bitmap cache by calling CMD_CLEARCACHE.

If the flash is blank (or erased using the CMD_FLASHERASE), it is recommended to use

CMD_FLASHPROGRAM to program the flash in order to achieve fastest programming speed. For Micron

MT25QL and Cypress S25FL-L series NOR flash, typical programming speed is about 900 kByte/s

(assume SPI clock 10MHz or higher in Single SPI mode).

4.5 Parallel RGB Interface

The RGB parallel interface consists of 29 signals - DISP, PCLK, VSYNC, HSYNC, DE, 8 signals each for R,

G and B.

A set of RGB registers configure the LCD operation and timing parameters.

REG_PCLK is used to select the display mode and clock divisor. The default value is 0, which means the

display scanout is disabled and all RGB signals output Low.

When REG_PCLK is set to 1, the display output will be in EXTSYNC mode, where the PCLK frequency is

controlled by REG_PCLK_FREQ from PLL2. The maximum PLL2 frequency is 228MHz. The PCLK

frequency can be set up to 96MHz to align with the optimized PCLK frequency of the selected LCD

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