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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

REG_DITHER enables colour dither. To improve image quality, the graphics engine applies a 2x2 color

dither matrix to output pixels. This option improves the half-tone appearance on displays, even on 1-

bit displays. Note that the dither function is not applicable to 2X mode (REG_PCLK_2X=1).

REG_OUTBITS gives the bit width of each colour channel. The default is 8/8/8 bits for each R/G/B

colour, giving total colour depth of 16,777,216 colours. A lower value means fewer bits are output for

that colour channel, allowing dithering on lower precision LCD displays. A typical lower precision LCD

has 6/6/6 bits for each R/G/B colour, giving total colour depth of 262,144 colours. For 6/6/6 bits

configuration, pins R2-R7, G2-G7 and B2-B7 will be used, while pins R0,R1,G0,G1,B0,B1 can be left

un-connected.

REG_SWIZZLE controls the arrangement of the output colour pins, to help PCB routing with different

LCD panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be

reversed. Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped.

Setting Bit 3 allows rotation to be enabled. If Bit 3 is set, then (R, G, B) is rotated right if bit 2 is one,

or left if bit 2 is zero.

REG_SWIZZLE

RGB PINS

b3 b2 b1 b0 R7, R6,

R5, R4,

R3, R2,

R1, R0

G7, G6,

G5, G4,

G3, G2,

G1, G0

B7, B6,

B5, B4,

B3, B2,

B1, B0

R[7:0]

G[7:0]

B[7:0]

R[0:7]

G[0:7]

B[0:7]

B[7:0]

G[7:0]

R[7:0]

B[0:7]

G[0:7]

R[0:7]

B[7:0]

R[7:0]

G[7:0]

B[0:7]

R[0:7]

G[0:7]

G[7:0]

R[7:0]

B[7:0]

G[0:7]

R[0:7]

B[0:7]

G[7:0]

B[7:0]

R[7:0]

G[0:7]

B[0:7]

R[0:7]

R[7:0]

B[7:0]

G[7:0]

R[0:7]

B[0:7]

G[0:7]

Table 4-13 REG_SWIZZLE RGB Pins Mapping

REG_HCYCLE, REG_HSIZE, REG_HOFFSET, REG_HSYNC0 and REG_HSYNC1 define the LCD horizontal

timings. Each register has 12 bits to allow programmable range of 0-4095 PCLK cycles. REG_VCYCLE,

REG_VSIZE, REG_VOFFSET, REG_VSYNC0 and REG_VSYNC1 define the LCD vertical timings. Each

Display

Parameter

Description

REG_HCYCLE

Total length of line (visible and non-visible) (in

PCLKs)

REG_HSIZE

THD

Length of visible part of line (in PCLKs)

REG_HOFFSET

THF + THP + THB

Length of non-visible part of line. Must be < TH -

THD

(in PCLK cycles)

REG_HSYNC0

THF

Horizontal Front Porch (in PCLK cycles)

REG_HSYNC1

THF + THP

Horizontal Front Porch plus Hsync Pulse width (in

PCLK cycles)

REG_VCYCLE

Total number of lines (visible and non-visible) (in

lines)

REG_VSIZE

TVD

Number of visible lines (in lines)

REG_VOFFSET

TVF + TVP + TVB

Number of non-visible lines. Must be < TV - TVD

(in lines)

REG_VSYNC0

TVF

Vertical Front Porch (in lines)

REG_VSYNC1

TVF + TVP

Vertical Front Porch plus Vsync Pulse width (in lines)

Table 4-14 Registers for RGB Horizontal and Vertical Timings

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