BT818Q-R datasheet(43/59 Pages) BRIDGETEK

43 / 59 page

BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

Address

(hex)

Bit

Reset

value

Description

302160h

REG_TOUCH_TRANSFORM

32 r/w

00010000h Touch-screen transform

coefficient (s15.16)

302164h

REG_TOUCH_TRANSFORM

32 r/w

00000000h Touch-screen transform

coefficient (s15.16)

302168h

REG_TOUCH_CONFIG

16 r/w

8381h

(BT818)

0381h

(BT817)

Touch configuration.

RTP/CTP select

RTP: short-circuit, sample clocks

CTP: I2C address, CTPM type,

low-power mode, touch host

mode

30216Ch

REG_CTOUCH_TOUCH4_X

16 r/o

- Extended mode: touch-screen

screen X data for touch 4

302170h

REG_EHOST_TOUCH_ACK

4 r/w

0 Touch host mode:

acknowledgement

302174h

REG_BIST_EN

1 r/w

0 BIST memory mapping enable

302178h

302187C

Reserved

- -

- Reserved

302184h

REG_ANA_COMP

8 r/w

0 Analogue control register

302188h

REG_SPI_WIDTH

3 r/w

0 QSPI bus width setting

Bit [2]: extra dummy cycle on

read

Bit [1:0]: bus width (0=1-bit,

1=2-bit, 2=4-bit)

30218Ch

REG_TOUCH_DIRECT_XY

REG_CTOUCH_TOUCH2_X

32 r/o

- Compatibility mode: Touch screen

direct (x-MSB16; y-LSB16)

conversions

Extended mode: touch-screen

screen data for touch 2 (x-

MSB16; y-LSB16)

302190h

REG_TOUCH_DIRECT_Z1Z

REG_CTOUCH_TOUCH3_X

32 r/o

- Compatibility mode: Touch screen

direct (z1-MSB16; z2-LSB16)

conversions

Extended mode: touch-screen

screen data for touch 3 (x-

MSB16; y-LSB16)

302194h

302560h

Reserved

- -

- Reserved

302564h

REG_DATESTAMP

128 r/o

- Stamp date code

302574h

REG_CMDB_SPACE

12 r/w

FFCh Command DL (bulk) space

available

302578h

REG_CMDB_WRITE

32 w/o

0 Command DL (bulk) write

30257Ch

REG_ADAPTIVE_FRAMERA

1 r/w

1 Reduce frame rate during

complex drawing

3025ECh

REG_PLAYBACK_PAUSE

1 r/w

0 Audio playback control. 0: play,

1: pause

3025F0h

REG_FLASH_STATUS

2 r/w

0 Flash status. 0: INIT, 1:

DETACHED, 2: BASIC, 3: FULL

3025F4h-

302608h

Reserved

- -

- Reserved

30260Ch

REG_UNDERRUN

32 r/o

- Line underrun counter

302610h

REG_AH_HCYCLE_MAX

12 r/w

0 Adaptive Hsync: maximum

horizontal total PCLK cycles. 0

means Adaptive Hsync is

disabled.

302614h

REG_PCLK_FREQ

16 r/w

0 Fractional PCLK

frequency/enable. Firmware sets

to 08A1h at boot.

BT818Q-R Scheda tecnica(PDF) 43 Page - Bridgetek Pte Ltd.

BT818Q-R Scheda tecnica(HTML) 43 Page - Bridgetek Pte Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Scheda tecnica Scarica

Link URL