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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

panel. If PCLK frequency is equal to or higher than system clock frequency (up to double the system

clock frequency), the REG_PCLK_2X needs to be 1 so that the graphics engine can send two pixels per

system clock to the EXTSYNC block. Note that in this 2X mode, the values loaded in the following

registers must be even: REG_HSIZE, REG_HOFFSET, REG_HCYCLE, REG_HSYNC0, REG_HSYNC1.

The PCLK frequency in EXTSYNC mode can be calculated as:

PLL2 frequency = 12MHz * REG_PCLK_FREQ[8:4]

PCLK frequency = PLL2 frequency / REG_PCLK_FREQ[3:0] / 2

REG_PCLK_FREQ[10:9] is determined by PLL2 frequency range:

00: 20 – 40 MHz

01: 40 – 80 MHz

10: 80 – 160 MHz

11: 160 – 228 MHz

Table 4-11 lists some of the valid PCLK frequency and REG_PCLK_FREQ values in EXTSYNC mode.

fpclk

(MHz)

REG_PCLK_

FREQ (hex)

fpclk

(MHz)

REG_PCLK_

FREQ (hex)

fpclk

(MHz)

REG_PCLK_

FREQ (hex)

fpclk

(MHz)

REG_PCLK_

FREQ (hex)

fpclk

(MHz)

REG_PCLK_

FREQ (hex)

D01

D12

D03

8B3

10.5

874

CF1

881

451

872

453

CE1

CF2

28.5

D34

19.5

8D4

8D1

871

CE3

443

8C1

8D2

892

16.5

8B4

7.5

454

8B1

D33

8D3

883

8A1

461

25.5

D14

452

4.5

D32

D13

441

13.5

894

891

8B2

22.5

CF4

Table 4-11 RGB PCLK Frequency in EXTSYNC mode

When REG_PCLK is set to 2 to 255, the display out is in pass-through mode, where the PCLK frequency

can be calculated as:

PCLK frequency = System Clock frequency / REG_PCLK

The BT817/8 system clock frequency is programmable. Some of the possible PCLK frequencies that

BT817/8 supports in pass-through mode are listed in Table 4-12.

REG_PCLK

System Clock Frequency (MHz)

60(default)

8.0

9.0

6.0

14.5

9.6

7.2

4.8

8.0

6.0

4.0

10.3

8.6

6.9

5.1

3.4

7.5

6.0

4.5

3.0

6.7

5.3

4.0

2.7

7.2

6.0

4.8

3.6

2.4

Table 4-12 RGB PCLK Frequency in Pass-Through mode

REG_PCLK_POL defines the clock polarity, with 0 for positive active clock edge, and 1 for negative clock

edge.

REG_CSPREAD controls the transition of RGB signals with respect to the PCLK active clock edge. When

REG_CSPREAD=0, R[7:0], G[7:0] and B[7:0] signals change following the active edge of PCLK. When

REG_CSPREAD=1, R[7:0] changes a PCLK clock early and B[7:0] a PCLK clock later, which helps

reduce the switching noise.

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