BT818Q-R datasheet(40/59 Pages) BRIDGETEK

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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

5 Memory Map

All memory and registers in the BT817/8 core are memory mapped in 22-bit address space with a 2-

bit SPI command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 is

reserved for Host Commands and 0'b11 undefined. The following are the memory space definition.

Start

Address

End

Address

Size

NAME

Description

00 0000h

0F FFFFh

1024 kB

RAM_G

General purpose graphics RAM

20 0000h

2F FFFFh

1024 kB

ROM

ROM codes, font table and bitmap

30 0000h

30 1FFFh

8 kB

RAM_DL

Display List RAM

30 2000h

30 2FFFh

4 kB

RAM_REG

Registers

30 8000h

30 8FFFh

4 kB

RAM_CMD

Command buffer

30 9800h

30 98FFh

128 B

RAM_ERR_REPORT

Coprocessor fault report RAM

30 B000h

30 B7FFh

2 kB

RAM_JTBOOT

Touch control codes

80 0000h

107F FFFFh

256 MB

FLASH

External NOR flash memory. Maximum

256MB. The address is used by internal

command only.

Table 5-1 BT817/8 Memory Map

Note 1: The addresses beyond this table are reserved and shall not be read or written unless

otherwise specified.

5.1 Registers

Table

5-2

shows

the

complete

list

the

BT817/8

registers.

Refer

BT81X_Series_Programming_Guide, Chapter 3 for details of the register function.

Address

(hex)

Bit

Reset

value

Description

302000

REG_ID

8 r/o

7Ch Identification register, always

reads as 7Ch

302004h

REG_FRAMES

32 r/o

0 Frame counter, since reset

302008h

REG_CLOCK

32 r/o

0 Clock cycles, since reset

30200Ch

REG_FREQUENCY

28 r/w

48000000 Main clock frequency (Hz).

Firmware sets to 60000000 at

boot.

302010h

REG_RENDERMODE

1 r/w

0 Rendering mode: 0 = normal, 1

= single-line

302014h

REG_SNAPY

11 r/w

0 Scanline select for RENDERMODE

302018h

REG_SNAPSHOT

1 r/w

- Trigger for RENDERMODE 1

30201Ch

REG_SNAPFORMAT

6 r/w

20h Pixel format for scanline readout

302020h

REG_CPURESET

3 r/w

2 Graphics, audio and touch

engines reset control. Bit2: audio,

bit1: touch, bit0: graphics

302024h

REG_TAP_CRC

32 r/o

- Live video tap crc. Frame CRC is

computed every DL SWAP.

302028h

REG_TAP_MASK

32 r/w

FFFFFFFFh Live video tap mask

30202Ch

REG_HCYCLE

12 r/w

224h Horizontal total cycle count

302030h

REG_HOFFSET

12 r/w

02Bh Horizontal display start offset

302034h

REG_HSIZE

12 r/w

1E0h Horizontal display pixel count

302038h

REG_HSYNC0

12 r/w

000h Horizontal sync fall offset

30203Ch

REG_HSYNC1

12 r/w

029h Horizontal sync rise offset

302040h

REG_VCYCLE

12 r/w

124h Vertical total cycle count

302044h

REG_VOFFSET

12 r/w

00Ch Vertical display start offset

302048h

REG_VSIZE

12 r/w

110h Vertical display line count

30204Ch

REG_VSYNC0

10 r/w

000h Vertical sync fall offset

302050h

REG_VSYNC1

10 r/w

00Ah Vertical sync rise offset

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