M95256-R datasheet(18/51 Pages) STMICROELECTRONICS

18 / 51 page

6.5

Read from Memory array (READ)

As shown in Figure 12, to send this instruction to the device, Chip select (S) is first driven low. The bits of the

instruction byte and address bytes are then shifted in, on Serial data input (D). The address is loaded into an

internal address register, and the byte of data at that address is shifted out, on Serial data output (Q).

Figure 12. Read from Memory array (READ) sequence

3 4 5 6 7 8 9 10

20 21 22 23 24 25 26 27

14 13

3 2 1 0

28 29 30

7 6 5 4 3

High Impedance

Data Out 1

Instruction

16-Bit Address

MSB

Data Out 2

Note:

Depending on the memory size, as shown in Table 5. Significant bits within the address bytes, the most

significant address bits are Don’t care.

If Chip select (S) continues to be driven low, the internal address register is incremented automatically, and the

byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be

continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.

The Read cycle is terminated by driving Chip select (S) high. The rising edge of the Chip select (S) signal can

occur at any time during the cycle.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

M95256-W M95256-R M95256-DF

Read from Memory array (READ)

DS4712 - Rev 22

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