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M95256-R Scheda tecnica(PDF) 26 Page - STMicroelectronics

Il numero della parte M95256-R
Spiegazioni elettronici  256-Kbit serial SPI bus EEPROM with high-speed clock
PDF  51 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95256-R Scheda tecnica(HTML) 26 Page - STMicroelectronics

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7
Power-up and delivery state
7.1
Power-up state
After power-up, the device is in the following state:
•
Standby power mode
•
Deselected (after power-up, a falling edge is required on Chip select (S) before any instructions can be
started)
•
Not in the Hold condition
•
The Write enable latch (WEL) is reset to 0
•
Write in progress (WIP) is reset to 0
The SRWD, BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are
non-volatile bits).
7.2
Initial delivery state
The device is delivered with the memory array and Identification page bits set to all 1s (each byte = FFh). The
Status register Write Disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.
M95256-W M95256-R M95256-DF
Power-up and delivery state
DS4712 - Rev 22
page 26/51



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