LPC2888 datasheet(16/34 Pages) PHILIPS

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LPC2880_LPC2888_1

Preliminary data sheet

Rev. 01 — 22 June 2006

16 of 34

Philips Semiconductors

LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

Programming the ﬂash in a running application is accomplished via a register interface on

the APB bus. The ﬂash module can generate an interrupt request when burning or erasing

is completed.

The ﬂash memory contains a buffer to allow for faster execution. Information is read from

the ﬂash 128 bits at a time. The buffer holds this entire amount, which can represent four

32-bit ARM instructions. These captured instructions can them be executed without ﬂash

read delays, improving system performance.

6.4.1 Features

• Flash access for processor execution and data read is via the AHB bus.

• Flash programming in a running application is via an APB register interface.

• Initial programming or reprogramming is can be accomplished from the USB port.

6.5 External memory controller

The LPC2880/LPC2888 External Memory Controller (EMC) is a multi-port memory

controller that supports asynchronous static memory devices such as RAM, ROM and

ﬂash, as well as dynamic memories such as Single Data Rate SDRAM. It complies with

ARM’s AMBA.

6.5.1 Features

• Dynamic memory interface support including Single Data Rate SDRAM.

• Asynchronous static memory device support including RAM, ROM, and ﬂash, with or

without asynchronous page mode.

• Low transaction latency.

• Read and write buffers to reduce latency and to improve performance.

• 8-bit and 16-bit static memory support.

• 16-bit SDRAM memory support.

• Static memory features include:

– Asynchronous page mode read.

– Programmable wait states.

– Bus turnaround delay.

– Output enable, and write enable delays.

– Extended wait.

– 2 MB address range with three chip selects.

• One chip select for synchronous memory and three chip selects for static memory

devices.

• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.

• Dynamic memory self-refresh mode controlled by software.

• Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is

typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per device.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

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