LPC2888 datasheet(18/34 Pages) PHILIPS

18 / 34 page

LPC2880_LPC2888_1

Preliminary data sheet

Rev. 01 — 22 June 2006

18 of 34

Philips Semiconductors

LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

All 105 Pending signals are presented to each of the ﬁve output logic blocks. Each output

logic block includes a set of four Interrupt Output Mask Registers, each set totalling 105

bits, that control whether each signal applies to that output. These are logically ANDed

with the corresponding Pending signals, and the 105 results in each logic block are

logically ORed to make the output of the block. The 525 results can be read in the

Interrupt Output Pending Registers.

Outputs 0 to 3 are routed to the Interrupt Controller, in which each can be individually

enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it

can serve as a wake-up generator. The ﬁve outputs can be read in the Output Register.

6.9 General purpose timers

The LPC2880/LPC2888 contains two fully independent general purpose timers. Each

timer is a 32-bit wide down counter with selectable prescaler. The prescaler allows either

the system clock to be used directly, or the clock to be divided by 16 or 256.

Two modes of operation are available, free-running and periodic timer. In periodic timer

mode, the counter will generate an interrupt at a constant interval. In free-running mode

the timer will overﬂow after reaching its zero value and continue to count down from the

maximum value.

6.9.1 Features

• Two independent 32-bit timers.

• Free-running or periodic operating modes.

• Generate timed interrupts.

6.10 Watchdog timer

The purpose of the Watchdog Timer is to interrupt and/or reset the microcontroller within a

reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog

will generate an interrupt or a system reset if the user program fails to reset the Watchdog

within a predetermined amount of time. Alternatively, it can be used as an additional

general purpose Timer.

The WDT clock increments a 32-bit Prescale Counter, the value of which is continually

compared to the value of the Prescale Register. When the Prescale Counter matches the

Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit

Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the

value in the Prescale Register plus one.

The value of the Timer Counter is continually compared to the values in two registers

called Match Register 0 and 1. When/if the value of the Timer Counter matches that of

Match Register 0 at a WDT clock edge, a signal ‘m0’ can be asserted to the Event Router,

which can be programmed to send an interrupt signal to the Interrupt Controller as a

result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT

clock edge, a signal ‘m1’ can be asserted to the CGU, which resets the chip as a result.

The CGU also includes a ﬂag to indicate whether a reset is due to a Watchdog time-out.

6.10.1 Features

• Optionally resets chip (via Clock Generation Unit) if not periodically reloaded.

LPC2888 Scheda tecnica(PDF) 18 Page - NXP Semiconductors

LPC2888 Scheda tecnica(HTML) 18 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Scheda tecnica Scarica

Link URL