MB95F118MS datasheet(53/64 Pages) FUJITSU

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MB95110M Series

(Continued)

(Vcc

= 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = −40 °C to + 85 °C)

*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.

*2 :

• Refer to “ (2) Source Clock/Machine Clock” for tMCLK.

• m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR0) .

• n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR0) .

• Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of

ICCR0 register.

• Standard-mode :

m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.

Setting of m and n limits the machine clock that can be used below.

(m, n)

= (1, 8)

: 0.9 MHz < tMCLK

≤ 1 MHz

(m, n)

= (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz

(m, n)

= (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz

(m, n)

= (1, 98)

: 0.9 MHz < tMCLK

≤ 10 MHz

• Fast-mode :

m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.

Setting of m and n limits the machine clock that can be used below.

(m, n)

= (1, 8)

: 3.3 MHz < tMCLK

≤ 4 MHz

(m, n)

= (1, 22) , (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz

(m, n)

= (6, 4)

: 3.3 MHz < tMCLK

≤ 10 MHz

Parameter

Sym-

bol

name

Condition

Value*2

Unit

Remarks

Min

Max

Data hold time

tHD;DAT

SCL0

SDA0

= 1.7 kΩ,

= 50 pF*1

⎯

At reception

Data setup time

tSU;DAT

SCL0

SDA0

tMCLK

− 20

⎯

At reception

SDA

↓→SCL↑

(at wake-up function)

tWAKEUP

SCL0

SDA0

Oscillation stabilization

wait time

+ 2 tMCLK − 20

⎯

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