MB95F118MS datasheet(32/64 Pages) FUJITSU

32 / 64 page

MB95110M Series

(Continued)

(AVss

= Vss = 0.0 V)

*1 : The value is 2.9 V when the low voltage detection reset is used.

*2 : P10, P50, P51, and P67 can switch the input level to either the “CMOS input level” or “hysteresis input level”.

The switching of the input level can be set by the input level selection register (ILSR).

*3 : Single clock products only

*4 : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. A bypass capacitor of VCC

pin must have a capacitance value higher than CS. For connection of smoothing capacitor CS, refer to the

diagram below.

Parameter

Symbol

Pin name

Condi-

tions

Value

Unit

Remarks

Min

Max

“L” level input

voltage

VIL

P10, P50,

P51, P67

Vss

− 0.3 0.3 Vcc

At selecting of CMOS input

level

VILA

⎯⎯

Vss

− 0.3 0.5 Vcc

Pin input at selecting of

AUTOMOTIVE input level

VILS

P00 to P07,

P10 to P15,

P20 to P24,

P30 to P37,

P50, P51,

P60 to P67,

PG1*3,

PG2*3

Vss

− 0.3 0.2 Vcc

Hysteresis input

VILM

RST, MOD

⎯

Vss

− 0.3 0.3 Vcc

CMOS input

(Flash memory product)

⎯

Vss

− 0.3 0.2 Vcc

Hysteresis input

(MASK ROM product)

Smoothing

capacitor

⎯⎯

0.1

1.0

µF*4

Operating

temperature

⎯⎯

− 40

+ 85

°C Other than MB95FV100D-103

+ 5

+ 35

°C MB95FV100D-103

• C pin connection diagram

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