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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MB90F482PF Scheda tecnica(PDF) 96 Page - fujitsu semiconductor |
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MB90F482PF Scheda tecnica(HTML) 96 Page - fujitsu semiconductor |
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96 / 113 page  MB90480/485 Series 96 (10) I/O Expanded Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C) *1 : CL is the load capacitance applied to pins for testing. *2 : tCP : See “ (1) Clock Timing Standards”. Notes : • AC ratings are for CLK synchronized mode. • Values on this table are target values. Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Serial clock cycle time tSCYC Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL 8 tCP*2 ns SCK ↓→SOT delay time tSLOV −80 + 80 ns −120 + 120 ns fcp = 8 MHz Valid SIN →SCK↑ tIVSH 100 ns 200 ns fcp = 8 MHz SCK ↑→valid SIN hold time tSHIX tCP*2 ns Serial clock “H” pulse width tSHSL External shift clock mode output pins : CL*1 = 80 pF + 1 TTL 4 tCP*2 ns Serial clock “L” pulse width tSLSH 4 tCP*2 ns SCK ↓→SOT delay time tSLOV 150 ns 200 ns fcp = 8 MHz Valid SIN →SCK↑ tIVSH 60 ns 120 ns fcp = 8 MHz SCK ↑→valid SIN hold time tSHIX 60 ns 120 ns fcp = 8 MHz |
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