 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
MB90F482PF Scheda tecnica(PDF) 23 Page - fujitsu semiconductor |
|
|
|||||||||||||||||||||||||||||
MB90F482PF Scheda tecnica(HTML) 23 Page - fujitsu semiconductor |
|
|
23 / 113 page  MB90480/485 Series 23 (Continued) Address Register name Abbreviated register name Read/ Write Resource name Initial value 68H Up/down count register ch0 UDCR0 R 8/16-bit up/down timer counter 0 0 0 0 0 0 0 0B 69H Up/down count register ch1 UDCR1 R 0 0 0 0 0 0 0 0B 6AH Reload/compare register ch0 RCR0 W 0 0 0 0 0 0 0 0B 6BH Reload/compare register ch1 RCR1 W 0 0 0 0 0 0 0 0B 6CH Counter control register lower digits ch0 CCRL0 R/W 0 X 0 0 X 0 0 0B 6DH Counter control register upper digits ch0 CCRH0 R/W 0 0 0 0 0 0 0 0B 6EH (Reserved area) 6FH ROM mirror function select register ROMM R/W ROM mirroring function - - - - - - 0 1 B 70H Counter control register lower digits ch1 CCRL1 R/W 8/16-bit up/down timer counter 0 X 0 0 X 0 0 0B 71H Counter control register upper digits ch1 CCRH1 R/W - 0 0 0 0 0 0 0B 72H Counter status register ch0 CSR0 R/W 0 0 0 0 0 0 0 0B 73H (Reserved area) 74H Counter status register ch1 CSR1 R/W 8/16-bit UDC 0 0 0 0 0 0 0 0B 75H (Reserved area) 76H* PWC control status register PWCSR0 R/W PWC timer (ch0) 0 0 0 0 0 0 0 0B 77H* 0 0 0 0 0 0 0 XB 78H* PWC data buffer register PWCR0 R/W 0 0 0 0 0 0 0 0B 79H* 0 0 0 0 0 0 0 0B 7AH* PWC control status register PWCSR1 R/W PWC timer (ch 1) 0 0 0 0 0 0 0 0B 7BH* 0 0 0 0 0 0 0 XB 7CH* PWC data buffer register PWCR1 R/W 0 0 0 0 0 0 0 0B 7DH* 0 0 0 0 0 0 0 0B 7EH* PWC control status register PWCSR2 R/W PWC timer (ch2) 0 0 0 0 0 0 0 0B 7FH* 0 0 0 0 0 0 0 XB 80H* PWC data buffer register PWCR2 R/W 0 0 0 0 0 0 0 0B 81H* 0 0 0 0 0 0 0 0B 82H* Dividing ratio control register DIVR0 R/W PWC (ch0) - - - - - - 0 0B 83H (Reserved area) 84H* Dividing ratio control register DIVR1 R/W PWC (ch1) - - - - - - 0 0B 85H (Reserved area) 86H* Dividing ratio control register DIVR2 R/W PWC (ch2) - - - - - - 0 0B 87H (Reserved area) 88H* Bus status register IBSR R I2C 0 0 0 0 0 0 0 0B 89H* Bus control register IBCR R/W 0 0 0 0 0 0 0 0B 8AH* Bus clock control register ICCR R/W - - 0 X X X X XB 8BH* Bus address register IADR R/W - X X X X X X XB 8CH* Bus data register IDAR R/W XXXXXXXXB 8DH (Reserved area) 8EH* µPG control status register PGCSR R/W µPG 0 0 0 0 0 - - -B 8FH to 9BH (Disabled) 9CH µDMA status register DSRL R/W µDMA 0 0 0 0 0 0 0 0B |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
