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MB90F482PF Scheda tecnica(PDF) 28 Page - fujitsu semiconductor |
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MB90F482PF Scheda tecnica(HTML) 28 Page - fujitsu semiconductor |
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28 / 113 page ![]() MB90480/485 Series 28 s PERIPHERAL RESOURCES 1. I/O Ports The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information from the I/O into the CPU, according to the setting of the corresponding port register (PDR) . The input/output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each port. The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A. (1) Port Data Registers *1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following operations. • Input mode Read : Reads the corresponding siganl pin level. Write : Writes to the output latch. • Output mode Read : Reads the value from the data register latch. Write : Outputs the value to the corresponding signal pin. *2 : The initial value of this bit is “11XXXXXXB” on MB90485 series. PDR0 Initial value Access Address : 000000H Undefined R/W *1 PDR1 Address : 000001H Undefined R/W *1 PDR2 Address : 000002H Undefined R/W *1 PDR3 Address : 000003H Undefined R/W *1 PDR4 Address : 000004H Undefined R/W *1 PDR5 Address : 000005H Undefined R/W *1 PDR6 Address : 000006H Undefined R/W *1 PDR7 Address : 000007H Undefined *2 R/W*1 PDR8 Address : 000008H Undefined R/W *1 PDR9 Address : 000009H Undefined R/W *1 PDRA Address : 00000AH Undefined R/W *1 76 5 4 3 2 1 0 P06 P07 P05 P04 P03 P02 P01 P00 76 5 4 3 2 1 0 P16 P17 P15 P14 P13 P12 P11 P10 76 5 4 3 2 1 0 P26 P27 P25 P24 P23 P22 P21 P20 P36 P37 P35 P34 P33 P32 P31 P30 76 5 4 3 2 1 0 76 5 4 3 2 1 0 P46 P47 P45 P44 P43 P42 P41 P40 P56 P57 P55 P54 P53 P52 P51 P50 76 5 4 3 2 1 0 76 5 4 3 2 1 0 P66 P67 P65 P64 P63 P62 P61 P60 P76 P77 P75 P74 P73 P72 P71 P70 76 5 4 3 2 1 0 76 5 4 3 2 1 0 P86 P87 P85 P84 P83 P82 P81 P80 P96 P97 P95 P94 P93 P92 P91 P90 76 5 4 3 2 1 0 76 5 4 3 2 1 0 PA3 PA2 PA1 PA0 |
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